1. Technical Field
The present disclosure relates to non-volatile memories in integrated circuits on semiconductor chips. The present disclosure relates more particularly to memories comprising UCP memory cells (Uniform Channel Program) that can be programmed and erased by the channel. The present disclosure relates more particularly to UCP memory cells with two transistors, comprising a selection transistor and a charge accumulation transistor such as a floating-gate transistor.
2. Description of the Related Art
FIG. 1 is a schematic cross-section of two UCP-type memory cells C11, C12, formed on a P-type substrate PW. Each memory cell C11, C12 comprises a floating-gate transistor FGT11, FGT12 and a selection transistor ST11, ST12. Each floating-gate transistor comprises a drain region n1 (D), a source region n2 (S), a floating gate FG, a control gate CG, and a channel region CH1 extending beneath the floating gate FG between the drain n1 and source n2 regions. Each selection transistor ST11, ST12 comprises a drain region n2 (D) common to the source region n2 of the corresponding floating-gate transistor FGT11, FGT12, a source region n3 (S), a gate SG, and a channel region CH2 extending beneath the gate SG between the drain n2 and source n3 regions. The two transistors ST11, ST12 share the same source region n3.
The regions n1, n2, n3 are generally formed by N-doping the substrate PW. The substrate is generally a P-type well formed in a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer NISO surrounding the entire well. The gates FG, SG are generally made of level-1 polycrystalline silicon, or “poly1”, and are formed on the substrate PW through layers of oxide D1, D2, the layer D1 being a tunnel oxide layer whereas the layer D2 is a gate oxide layer. The control gate CG is generally made of level-2 polycrystalline silicon, or “poly2”, and is formed on the floating gate FG through an oxide layer D3.
The two memory cells are covered with a dielectric insulating material D0, which can also be oxide SiO2. The drain regions n1 of the transistors FGT11, FGT12 are linked to a same bit line BL through a contact C1 passing through the insulating material D0 to reach an intermediate conductor T1 formed in a first level of metal, or “metal1”, and through a conductive via V1 passing through the insulating material D0 to link the conductor T1 to the bit line BL, formed in a second level of metal, or “metal2”. The source region n3 common to the two transistors ST11, ST12 is linked to a source line SL through a contact C2 passing through the insulating material D0, the source line SL being for example formed in the first level of metal.
Table REF1 in Appendix 1 describes in relation with FIG. 2 the voltages applied to the memory cells C11, C12, FIG. 2 representing their equivalent wiring diagram. Table RD1 in Appendix 1 describes in relation with FIG. 3 values of voltages applied to the memory cells when reading the memory cell C11. The column “Ref.” describes the reference allocated to each voltage value and the column “E.g.” describes examples of voltage values. “GND” is the ground potential, i.e., the potential of the wafer WF, generally 0V.
Therefore, when reading the cell C11, the selection transistor ST12 receives the cutoff voltage Voff and is not on. A current (represented by arrows in FIG. 3) flows in the channel region CH1 of the transistor FGT11 and in the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11 which is itself representative of a programmed or erased state of the transistor, which depends on a quantity of electric charges stored in its floating gate. This current is sensed by a sense amplifier not represented in the figure, that supplies a binary datum stored by the cell C11.
The selection transistor ST12 being cut off by the voltage Voff, the value of the so-called “non-reading” voltage Vnrd applied to the floating-gate transistor FGT12 is not significant since this transistor is isolated from the source region n3 by the transistor ST12. In Table RD1, this voltage is chosen equal to the voltage VB1 of the substrate PW, here the potential GND.
The cells C11, C12 offer the advantage of being capable of being programmed or erased by applying a pair of determined voltages to the substrate PW and to the control gate CG of their transistor FGT11, FGT12, this programming and erasing mode being referred to as “channel programming and erasing.” For a better understanding, Table ER1 in Appendix 1 describes values of voltages applied to the memory cells when erasing the cell C11. Table PG1 in Appendix 1 describes values of voltages applied to the memory cells when programming the cell C11. “HZ” designates a floating potential (open circuit).
The charge transfer from the substrate PW to the floating gate FG (programming) or from the floating gate to the substrate (erasing) is performed without going through the selection transistor ST11, as is the application of the high difference in potential (here 15V) enabling this charge transfer. As a result, the programming, erasing, and reading steps are conducted with low-value voltages, using the difference in potential between the substrate and the control gate of the floating-gate transistors. Therefore, the selection transistors ST11, ST12 do not undergo any high voltages, which allows for simple memory cells C11, C12 that are small in terms of semiconductor surface.
Despite the advantages such UCP memory cells offer, it may be desirable to provide a means of further reducing their size, so as to reduce the size of a memory array comprising a plurality of such memory cells. It may also be desirable to provide a compact memory structure.